EDMA Notes

http://e2e.ti.com/support/embedded/linux/f/354/t/140290.aspx?pi36987=1

http://e2e.ti.com/support/embedded/linux/f/354/p/104964/506774.aspx#506774

In the source file arch\arm\mach-omap2\devices.c, array ti816x_dma_rsv_chans[][2] is used to reserve various DMA channels to the shadow regions of all other masters other than ARM.

static const s16 ti816x_dma_rsv_chans[][2] = {
        /* (offset, number) */
        {0, 4},
        {26, 6},
        {48, 4},
        {56, 8},
        {-1, -1}
};

The first entry means 4 channels from channel '0' i.e. channels '0-3' will be reserved for usage of other masters (for eg. DSP).

It is assumed that if a particular channel number x is reserved for a particular master then the TCC x is also reserved for that same master. All drivers and applications running on all masters must keep this in mind and be programmed.

In the source file arch\arm\mach-omap2\devices.c, array ti816x_dma_rsv_slots[][2] is used to reserve various PARAM sets (slot) to the shadow regions of all other masters other than ARM.

static const s16 ti816x_dma_rsv_slots[][2] = {
        /* (offset, number) */
        {0, 4},
        {26, 6},
        {48, 4},
        {56, 8},
        {64, 127},
        {-1, -1}
};

The first entry means 4 slots from slot '0' i.e. slots '0-3' will be reserved for usage of other masters (for eg. DSP).

Note 1: DMA channels and PaRAM Sets are one-to-one mapped, meaning thereby DMA channel X can ONLY use PaRAM Set X for its working.

Note 2: A DMA/QDMA channel also require a TCC for correct functioning. By default, DMA channels and TCCs are one-to-one mapped, meaning thereby DMA channel Y can ONLY use TCC Y for its working. (No such constraint is there for QDMA channels.)

Array ti816x_queue_priority_mapping[][2] can be used to change the default event queue priorities. This array is an array of structures having the first structure member as the event queue number and the second structure member as the priority. '0' is the highest priority, '1' is the second highest and so on.

static const s8 ti816x_queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
        {0, 0},
        {1, 1},
        {2, 2},
        {3, 3},
        {-1, -1}
};

(a) Determine the type of channel (QDMA or DMA) to be used.

(b) Channel mapping

(i) If using a QDMA channel, program the DQCHMAP with the parameter set number to which the channel maps and the trigger word.

(ii) If using a DMA channel, program the DCHMAP with the parameter set number to which the channel maps.

(c) If the channel is being used in the context of a shadow region, ensure the DRAE/DRAEH for the region is properly set up to allow read write accesses to bits in the event registers and interrupt registers in the Shadow region memory map. The subsequent steps in this process should be done using the respective shadow region registers.

(d) Determine the type of triggering used.

(i) If external events are used for triggering (DMA channels), enable the respective event in EER/EERH by writing into EESR/EESRH.

(ii) If QDMA Channel is used, enable the channel in QEER by writing into QEESR.

(e) Queue setup

(i) If a QDMA channel is used, set up the QDMAQNUM to map the channel to the respective event queue.

(ii) If a DMA channel is used, set up the DMAQNUM to map the event to the respective eventqueue.

(a) Program the PaRAM set number associated with the channel. Note that if it is a QDMA channel, the PaRAM entry that is configured as trigger word is written to last. Alternatively, enable the QDMA channel (step 1-b-ii above) just before the write to the trigger word. See Section 5.3 for parameter set field setups for different types of transfers. See the sections on chaining and interrupt completion on how to set up final/intermediate completion chaining and/or interrupts.

(a) Enable the interrupt in the IER/IERH by writing into IESR/IESRH.

(b) Ensure that the EDMA3CC completion interrupt (either the global or the shadow region interrupt) is enabled properly in the device interrupt controller.

(c) Ensure the EDMA3CC completion interrupt (this refers to either the Global interrupt or the shadow region interrupt) is enabled properly in the Device Interrupt controller.

(d) Set up the interrupt controller properly to receive the expected EDMA3 interrupt.

(a) This step is highly dependent on the event trigger source:

(i) If the source is an external event coming from a peripheral, the peripheral will be enabled to start generating relevant EDMA3 events that can be latched to the ER transfer.

(ii) For QDMA events, writes to the trigger word (step 2-a above) will initiate the transfer.

(iii) Manually triggered transfers will be initiated by writes to the Event Set Registers (ESR/ESRH).

(iv) Chained-trigger events initiate when a previous transfer returns a transfer completion code equal to the chained channel number.

(a) If the interrupts are enabled as mentioned in step 3 above, then the EDMA3CC will generate a completion interrupt to the CPU whenever transfer completion results in setting the corresponding bits in the interrupt pending register (IPR/IPRH). The set bits must be cleared in the IPR\IPRH by writing to corresponding bit in ICR\ICRH.

(b) If polling for completion (interrupts not enabled in the device controller), then the application code can wait on the expected bits to be set in the IPR\IPRH. Again, the set bits in the IPR\IPRH must be manually cleared via ICR\ICRH before the next set of transfers is performed for the same transfer completion code values.